Using both edges of the clock means doubling the clock frequency. Both asynchronous set (sn) and reset (rn) can be turned on or off using generic parameters.
Double edge triggered flip flop wiki code#
The synthesizable VHDL source code of the pde dff is shown in listing 2. 2, asynchronous set and reset are possible. The outputs of the flipflops are connected via an XOR gate. The pde dff consists of 2 cross-coupled flipflops, one triggered by the rising and the other one triggered by the falling edge of the clock signal c. Note that synthesis tools will transform the multiplexers into XOR gates.įig. Therefore we need another way to model dual-edge behavior.Īlthough dual-edge behavior is not supported by VHDL, synthesis and the cell libraries, a dual-edge flipflop can be described as shown in fig. Only few are capable of handling such a description. In VHDL dual-edge behavior can be described as shown in listing 1, but most synthesis tools do not support this. There are two problems if dual-edge behavior is desired: For odd divisors the divided clock signal has to be switched at the falling edge of the fast clock, to get the same length for the low and the high period. If a transmitter wants so send a FM0 encoded data stream and runs only at the symbol frequency, the output signal has to be switched with the rising edge of clock and additionally with the falling edge, if zero is transmitted.Īnother example for dual-edge behavior are clock dividers. Another signal switch is done in the middle of the symbol, if zero has to be transmitted. With FM0 encoding always the signal switches at the begin of every symbol. But the signal frequency might be higher than the symbol frequency.įM0 encoding (fig.
One example is low-power signal processing, where all state machines should run at the symbol frequency to avoid unnecessary switching. not synthesizable dual-edge behavior in VHDL Although this is a good design practice in some special cases it might be helpful to use both edges. One important design rule is to use only one edge of the clock signal.
0 kommentar(er)
